Receivers in a wireless communication apparatus include a direct-conversion type receiver as shown in FIG. 1. Referring to FIG. 1, radio-frequency signals received by an antenna 201 are amplified by a low-noise amplifier (hereinafter abbreviated to “LNA”) 202. Practically, a duplexer, a radio-frequency filter (a broad-band filter that is not used to limit a channel band), and the like are provided between the antenna 201 and the LNA 202. However, they are omitted from the drawings.
The entire receiving band, which is not a channel, is extracted from the signals amplified in the LNA202 by a radio-frequency band-pass filter (hereinafter abbreviated to “RF BPF”) 203, so that signals in bands other than the receiving band, such as a transmitting signal transmitted by the wireless communication apparatus itself, are suppressed. The output of the RF BPF 203 is inputted to a quadrature demodulator circuit 204. The quadrature demodulator circuit 204 demodulates the input signal and outputs an I component that is an in-phase component and a Q component that is a quadrature component.
The quadrature demodulator circuit 204 has a buffer amplifier 221, multiplier units 222 and 223 as balanced mixers, a quadrature signal generator 224, and a local oscillator 225. This type of devices is well-known, and detailed explanation thereof is therefore omitted. The I component and the Q component demodulated by the quadrature demodulator circuit 204 are inputted to base band filters (hereinafter abbreviated to “BB BPF”) 205 and 206, where those components are respectively limited in band. Each of the BB BPFs 205 and 206 is a band-pass filter (BPF). This is not only for the purpose of suppressing adjacent channel components to remove an DC offset produced in the quadrature demodulator circuit 204, but also for the purpose of suppressing low-frequency components that are very close to a direct current. Hereinafter, this type of filter is referred to as a channel filter.
The I component and the Q component limited in band by the channel filters 205 and 206 are inputted into a base band circuit 207. The base band circuit 207 has variable gain amplifiers (hereinafter abbreviated to “VGA”) 208, 209, 210, 211, 212, and 213, A/D converters 215 and 216, and a gain controller 214. In the base band circuit 207, the I component and the Q component limited in band are amplified by the VGAs 208-210 and 211-213, respectively, to certain levels at which an optimum conversion process can be performed in the subsequent A/D converters 215 and 216. In FIG. 1, the VGAs are illustrated as having a three-stage arrangement. However, the VGAs may have any arrangement as long as they have one or more stages. Furthermore, the positional relationships between the channel filter 205 and the VGAs 208-210 and between the channel filter 206 and the VGAs 211-213 are not limited to the example shown in FIG. 1. Moreover, each of the channel filters 205 and 206 may be divided into a plurality of stages and disposed between the VGAs.
The I component output and the Q component output at the final stage of the VGAs are subjected to A/D conversion in the A/D converters 215 and 216, respectively, and transmitted to a subsequent digital signal processing circuit (see FIG. 2).
FIG. 2 is a diagram showing the digital signal processing circuit 100. A digital amplitude calculator 303 calculates an average amplitude of the signals, for example, within one slot in CDMA or TDMA from the digital I signal and Q signal transmitted from the base band circuit 207 shown in FIG. 1. Subsequently, a subtractor 302 computes a difference between the calculation result of the average amplitude and a targeted reference amplitude. The computed difference is inputted into a digital gain control data generator 301. The digital gain control data generator 301 generates gain control data for controlling gains of the VGAs from the computed difference.
The gain control data are transmitted to the gain controller 214 shown in FIG. 1. The gain controller 214 controls the gains of the VGAs 208-210 and 211-213 based on the gain control data. In this case, the gain control data may be analog signals or digital signals. Furthermore, FIG. 1 shows that all of the VGAs are collectively provided in the base band circuit 207. However, the LNA 202 or the buffer amplifier 221 can also be used as a VGA. In such a case, as a matter of course, the gain of the LNA 202 or the buffer amplifier 221 is controlled by the gain control data from the gain controller 214.
With the above arrangement and operation, the signal levels of the I component and the Q component are automatically adjusted so that the levels of the input signals to the A/D converters 215 and 216 optimally fall within dynamic ranges of the A/D converters 215 and 216 (AGC).
An example of AGC in this type of receiver is disclosed in Patent Document 1 (Japanese laid-open patent publication No. 2001-168664).
In the existing communication systems such as CDMA and W-CDMA, direct-conversion type receivers as shown in FIG. 1 have worked well without any problems. However, higher-speed transmission systems, such as HSDPA (High Speed Downlink Packet Access) system in 3GPP (Third Generation Partnership Project), have been developed progressively in recent years. The HSDPA system adopts not only QPSK demodulation but also downstream modulation such as 16-QAM. Furthermore, it requires high-speed data transfer having an extremely low spreading rate. In order to meet such demands, it is necessary to require a higher degree of demodulation precision at a receiving end of a communication terminal device.
For example, while an EVM (Error Vector Magnitude) of about 15% to about 20% has been required in the conventional technology, the HSDPA system is considered to require an EVM of 5% or less. It is difficult to implement such high-precision demodulation when an analog channel filter is used. For example, it is not easy to maintain an EVM of 5% or less because of variations of characteristics or time-varied characteristics of parts comprising an analog channel filter.
Thus, there is considered a method of forming channel filters by digital filters and disposing them on the downstream side of the A/D converters. Because a digital filter does not cause variations of characteristics or time-varied characteristics of parts, a high-precision demodulation can be achieved.
An example in which the channel filters are formed by digital filters is shown in FIG. 3. In FIG. 3, equivalent parts to those shown in FIG. 1 are denoted by the same reference numerals.
FIG. 3 shows an example in which the channel filters 205 and 206 shown in FIG. 1 are respectively replaced with digital filters (DLPF) 217 and 218, which are disposed on the downstream side of the A/D converters 215 and 216. Here, the channel filters for digital processing are formed by low-pass filters. However, those channel filters may be high-pass filters for removing a DC offset. Furthermore, low-pass filters for preventing aliasing caused by A/D conversion may be left on the upstream side of the A/D converters 215 and 216.
FIG. 4 shows an example of frequency characteristics of the digital filters 217 and 218. As shown in FIG. 4, the frequency characteristics exhibit that signals in bands for a desired channel to be received are straightly passed as much as possible while signals in bands for the rest of the channels including an adjacent channel are suppressed. Usually, the frequency characteristics should be infinitely close to root cosine roll-off characteristics in order to reduce the EVM. Practically, such a design is possible.
FIGS. 5A and 5B show an example of level changes of a desired wave and an interference wave in an adjacent channel in a case where those waves pass through a digital filter having frequency characteristics shown in FIG. 4. Even though the interference wave in the adjacent channel is extremely greater than the desired wave on the input side of the digital channel filters 217 and 218 as shown in FIG. 5A, the interference wave is remarkably suppressed by the frequency characteristics of the digital channel filters 217 and 218 after the waves have passed through the digital channel filters 217 and 218 as shown in FIG. 5B. Accordingly, the level of the interference wave becomes lower than that of the desired wave.
Thus, the level of the interference wave greatly changes between before and after the digital channel filters 217 and 218. If the digital I signal and Q signal in which an interference wave have been suppressed are inputted to the digital signal processing circuit 100 shown in FIG. 2, then the digital amplitude calculator 303 underestimates the interference wave to compute an average amplitude, as compared to the case the digital signal processing circuit 100 is disposed immediately after the A/D converters 215 and 216. This means that the difference between the computed average amplitude and the reference amplitude becomes smaller than the actual difference. As a result, excessive gain control data is generated in the digital signal processing circuit 100, causing excessive gains in the VGA.
At that time, there may arise a problem that the amplitudes at the inputs of the A/D converters 215 and 216 deviate from an appropriate input range of the A/D converters 215 and 216 due to the interference wave in the adjacent channel. In such a situation, the A/D converters 215 and 216 are not expected to work correctly. As a result, the A/D converters 215 and 216 do not correctly function as receivers.
For AGC control, a receiver disclosed in Patent Document 1 detects an average amplitude of input signals to a digital channel filter and generates a AGC control signal in accordance with a difference between the detected average amplitude and a reference value. Thus, that receiver does not detect an average amplitude of output signals of the digital channel filter to perform AGC control.
It is an object of the present invention to provide a receiving amplitude correction circuit capable of controlling an A/D converter so as to work correctly to maintain a function of a receiver in a case where, using a digital channel filter as a channel filter, an AGC control is performed in accordance with an average amplitude of output signals of the digital channel filter, a receiving amplitude correction method, and a receiver using the same.